Current demands for high density and performance associated with ultra large-scale integrated circuits require sub-micron features, increased transistor and circuit speeds, and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface features' critical dimensions (CD), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device, as well as their cross-sectional shape (“profile”) are becoming increasingly important. Deviations of a feature's critical dimension and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature's critical dimension and profile may indicate processing problems, such as stepper defocusing or photo-resist loss due to over-exposure.
Thus, the critical dimension and profile values, especially gate length and gate profile, and their variation from design dimensions, are important indicators of the accuracy and stability of the photo-resist and etch processes. Most of the prior art concentrate efforts on the control of critical dimension, and fewer target gate profile control. MOS device drive current is sensitive to gate critical dimension and gate profile, however, and hence stability of controlling gage formation contributes to overall chip performance improvement.
Although equipment is available for measuring device gate critical dimensions and profiles, such equipment generally does not provide immediate feedback to the photolithography process to reduce variations, and the results of conventional inspections are not typically used to adjust subsequent etch processing. Furthermore, due to process variations, gate critical dimension and profile may be affected by factors unknown to designers, making it difficult to have a universal setting for process control.
There exists a need, therefore, for a simple, cost-effective methodology and system for gate formation control without a significant reduction in production throughput.